IDT74LVC08A Datasheet, PDF (1/5 Pages) Integrated Device Technology – 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O

IDT74LVC08A
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE
3.3V CMOS
QUADRUPLE 2-INPUT
POSITIVE-AND GATE
WITH 5 VOLT TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC08A
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, and TSSOP packages
DESCRIPTION:
This quadruple 2-input positive-AND gate is built using advanced dual
metal CMOS technology. The LVC08A device performs the Boolean
function Y = A • B or Y = A + B in positive logic.
The LVC08A has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1A
1
14
VCC
1B
2
13
4B
A
1Y
3
12
4A
Y
2A
4
11
4Y
B
2B
5
10
3B
2Y
6
9
3A
GND 7
8
3Y
SOIC/ SSOP/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
Description
xA, xB
xY
Data Inputs
Data Outputs
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©2000 Integrated Device Technology, Inc.
FUNCTION TABLE (EACH GATE)⁽¹⁾
Inputs
xA
xB
H
H
L
X
X
L
Output
xY
H
L
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
FEBRUARY 2000
1
DSC-4585/1