IDT74FCT810BT Datasheet, PDF (1/6 Pages) Integrated Device Technology – FAST CMOS BUFFER/CLOCK DRIVER

Integrated Device Technology, Inc.
FAST CMOS
BUFFER/CLOCK DRIVER
IDT54/74FCT810BT/CT
FEATURES:
• 0.5 MICRON CMOS technology
• Guaranteed low skew < 600ps (max.)
• Very low duty cycle distortion < 700ps (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: –32mA IOH, 48mA IOL
• Two independent output banks with 3-state control
– One 1:5 Inverting bank
– One 1:5 Non-Inverting bank
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, CERPACK and
LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT810BT/CT is a dual bank inverting/ non-
inverting clock driver built using advanced dual metal CMOS
technology. It consists of two banks of drivers, one inverting
and one non-inverting. Each bank drives five output buffers
from a standard TTL-compatible input. The IDT54/
74FCT810BT/CT have low output skew, pulse skew and
package skew. Inputs are designed with hysteresis circuitry
for improved noise immunity. The outputs are designed with
TTL output levels and controlled edge rates to reduce signal
noise. The part has multiple grounds, minimizing the effects of
ground inductance.
FUNCTIONAL BLOCK DIAGRAMS
PIN CONFIGURATIONS
OEA
INA
OEB
INB
5
OA1-OA5
5
OB1-OB5
3103 drw 01
VCC
1
20
VCC
OA1
2
19
OB1
OA2
3
18
OB2
OA3
GND
OA4
OA5
4
P20-1
17
5
D20-1
SO20-2
16
6
SO20-7
SO20-8
15
&
7
E20-1
14
OB3
GND
OB4
OB5
GND
8
13
GND
OEA
9
12
OEB
INA
10
11
INB
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
3103 drw 02
INDEX
OA3
GND
OA4
OA5
GND
32
20 19
4
1
18
5
17
6
L20-2
16
7
15
8
14
9 10 11 12 13
OB2
OB3
GND
OB4
OB5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
9.4
LCC
TOP VIEW
3103 drw 03
OCTOBER 1995
DSC-4646/3
1