IDT74FCT543AT_06 Datasheet, PDF (1/7 Pages) Integrated Device Technology – FAST CMOS OCTAL LATCHED TRANSCEIVER

IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT543AT/CT/DT
FEATURES:
• A, C, and D grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 64mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Power off disable outputs permit "live insertion"
• Available in SOIC and QSOP packages
DESCRIPTION:
The FCT543T is a non-inverting octal transceiver built using an advanced
dual metal CMOS technology. This device contains two sets of eight D-type
latches with separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must be low in order
to enter data from A0–A7 or to take data from B0–B7, as indicated in the
Function Table. With CEAB low, a low signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent low-to-
high transition of the LEAB signal puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With CEAB and OEAB both
low, the 3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
FUNCTIONAL BLOCK DIAGRAM
DQ
LE
A0
DETAIL A
B0
QD
LE
A1
A2
A3
A4
A5
A6
A7
OEBA
CEBA
LEBA
DETAIL A x 7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2006 Integrated Device Technology, Inc.
B1
B2
B3
B4
B5
B6
B7
OEAB
CEAB
LEAB
JUNE 2006
DSC-5489/6