IDT74FCT3932-100 Datasheet, PDF (1/9 Pages) Integrated Device Technology – 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
Integrated Device Technology, Inc.
COMMERC_IDIA_TL ₇TE₄M_FP_CER_TA₃T₉UR₃E₂R_-1A₀NG₀ES
3.3V LOW SKEW PLL-BASED
IDT74FCT32932-100
CMOS CLOCK DRIVER
ADVANCE INFORMATION
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew
• 16 programmable frequency configurations
• 17 3-state outputs: ±24 mA FCT3932
±8 mA FCT32932
• Output configuration:
BANK1: 4 outputs
BANK2: 8 outputs
BANK3: 5 outputs
• Dedicated feedback output (Q_FB)
• Maximum output frequency: 100MHz
• VCC = 3.3V ±0.3V
• Inputs can be driven from 3.3V or 5V components
• Available in 48 SSOP, TSSOP packages
• Suited to SDRAM applications
DESCRIPTION:
The FCT3932 uses phase-lock loop technology to lock the
frequency and phase of the feedback to the input reference
clock. It provides a large number of low skew outputs that are
configurable in 16 different modes using the CNTRL 1-4
inputs. A dedicated output, Q_FB, is provided to supply the
PLL feedback and it should be connected to the FEEDBACK
input. Q_FB is located adjacent to FEEDBACK to minimize
the delay in the feedback path. In order to offset any delay in
the output path from the FCT3932 output to a receiving device,
feedback path delay should be made to match this output path
delay.
The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The FCT3932 requires no external
loop filter components.
The FCT3932 provides 17 outputs grouped in 3 banks with
individual 3-state control and an additional dedicated feed-
back output with no disable. Connecting Q_FB to FEEDBACK
ensures uninterrupted PLL operation when all outputs are
disabled.
Individual bank 3-state allows users to disable unused
outputs in order to limit power dissipation or minimize switch-
ing noise. It also allows users to shut down outputs in low
power modes while maintaining phase lock.
The FCT3932 provides a LOCK pin that goes high when the
device is phase-locked.
The user can bypass the PLL for testability purposes by
deasserting PLL_EN. In this "test" mode, the input frequency
is not limited to the specified range.
RST The FCT3932 provides an asynchronous reset input, ,
which resets all outputs. This initializes all internal registers so
that outputs start up in a known state.
APPLICATIONS:
SDRAM DIMM Clock, Caches, high speed microproces-
sors, motherboard clock distribution to DIMMs.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
REF_IN
LOCK
Phase/Freq.
Detector
Charge
Pump &
Loop Filter
Voltage
Controlled
Oscillator
PLL_EN
01
Mux
C
O
N
T
R
O
L
CNTRL1-4
OE1
OE2
OE3
Q41-4
(BANK 1)
Q81-8
(BANK 2)
Q51-5
(BANK 3)
Q_FB
RST
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
9.9
9.9
3267 drw 01
NOVEMBER 1996
DSC-3267/2
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