IDT74FCT3574 Datasheet, PDF (1/7 Pages) Integrated Device Technology – 3.3V CMOS OCTAL D REGISTERS (3-STATE)

3.3V CMOS OCTAL D
REGISTERS (3-STATE)
IDT54/74FCT3574/A
ADVANCE INFORMATION
Integrated Device Technology, Inc.
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• 25 mil Center SSOP Packages
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The FCT3574/A are 8-bit registers built using an advanced
dual metal CMOS technology. These registers consist of
eight D-type flip-flops with a buffered common clock and
buffered 3-state output control. When the output (OE) input is
LOW, the eight outputs are enabled. When the OE input is
HIGH, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements
of the D inputs is transferred to the O outputs on the LOW-to-
HIGH transition of the clock input.
FUNCTIONAL BLOCK DIAGRAM
D0
D1
CP
CP ^D
Q
CP ^D
Q
D2
CP ^D
Q
D3
CP ^D
Q
D4
CP ^D
Q
D5
CP ^D
Q
D6
CP ^D
Q
D7
CP ^D
Q
OE
O0
O1
PIN CONFIGURATION
OE ¹
20
VCC
D0
2
19
O0
D1
3
18
O1
D2 4 _P20-1 17
O2
D3 5 ^D20-1 16
O3
D4
6
SO20-2
&
15
O4
D5
7 _SO20-7 14
O5
D6
8
13
O6
D7
9
GND ₁₀
12
O7
11
CP
DIP/SOIC/SSOP
TOP VIEW
O2
O3
O4
O5
O6
O7
3095 drw 01
PIN DESCRIPTION
Pin Names
DN
CP
ON
ON
OE
Description
D flip-flop data inputs
Clock Pulse for the register. Enters data on
LOW-to-HIGH transition.
3-state outputs, (true)
3-state outputs, (inverted)
Active LOW 3-state Output Enable input
3095 tbl 01
3095 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
8.14
AUGUST 1995
DSC-4650/-
1