IDT74FCT3573 Datasheet, PDF (1/7 Pages) Integrated Device Technology – 3.3V CMOS OCTAL TRANSPARENT LATCHES

Integrated Device Technology, Inc.
3.3V CMOS OCTAL
TRANSPARENT
LATCHES
IDT54/74FCT3573/A
ADVANCE INFORMATION
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• 25 mil Center SSOP Packages
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The FCT3573/A are octal transparent latches built using an
advanced dual metal CMOS technology.
These octal latches have 3-state outputs and are intended
for bus oriented applications. The flip-flops appear transpar-
ent to the data when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the set-up time is latched. Data
appears on the bus when the Output Enable (OE) is LOW.
When OE is HIGH, the bus output is in the high-impedance
state.
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
3093 drw 01
PIN CONFIGURATION
FUNCTION TABLE ⁽¹⁾
OE 1
20
VCC
D0 2
19
O0
D1
3
18
P20-1
O1
D2
4 _D20-1 17
O2
D3 5 SO20-2 16
O3
D4 6
& ₁₅
O4
SO20-7
D5 7
14
O5
D6 8
13
O6
Inputs
DN
LE
H
H
L
H
X
X
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
Outputs
OE
ON
L
H
L
L
H
Z
3093 tbl 02
D7
GND
9
12
10
11
DIP/SOIC/SSOP
TOP VIEW
O7
LE
3093 drw 02
DEFINITION OF FUNCTIONAL TERMS
Pin Names
DN
LE
OE
Data Inputs
Description
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
ON
3-State Outputs
ON
Complementary 3-State Outputs
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3093 tbl 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
©1995 Integrated Device Technology, Inc.
8.13
DSC-4648/-
1