IDT74ALVCH16903 Datasheet, PDF (1/13 Pages) Integrated Device Technology – 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HOLD

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT UNIVERSAL
BUS DRIVER WITH PARITY
CHECKER, DUAL 3-STATE
OUTPUTS AND BUS-HOLD
IDT74ALVCH16903
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Symbol
Description
Max
Unit
VTERM⁽²⁾ Terminal Voltage with Respect to GND –0.5 to +4.6
V
VTERM⁽³⁾ Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
(Outputs Only)
TSTG Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
±50
mA
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
Continuous Current through each
ISS
VCC or GND
±100
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. This value is limited to 4.6V maximum.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter⁽¹⁾
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance VOUT = 0V
7
9
pF
COUT
I/O Port Capacitance VIN = 0V
7
9
pF
NOTE:
1. As applicable to the device type.
DESCRIPTION:
This 12-bit universal bus driver is built using advanced dual metal CMOS
technology. This device has dual outputs and can operate as a buffer or an
edge-triggered register. In both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies. The YERR output, which is
produced one cycle after APAR, is open drain.
MODE selects one of the two data paths. When MODE is low, the device
operates as an edge-triggered register. On the positive transition of the clock
(CLK) input and when the clock-enable (CLKEN) input is low, data setup at the
A inputs is stored in the internal registers. On the positive transition of CLK and
when CLKEN is high, only data setup at the 9A-12A inputs is stored in their
internal registers. When MODE is high, the device operates as a buffer and data
at the A inputs passes directly to the outputs. The 11A/YERREN serves a dual
purpose; it acts as a normal data bit and also enables YERR data to be clocked
into the YERR output register.
When used as a single device, parity output enable (PAROE) must be tied
high; when parity input/output (PARI/O) is low, even parity is selected and when
PARI/O is high, odd parity is selected. When used in pairs and PAROE is low,
the parity sum is output on PARI/O for cascading to the second ALVCH16903.
When used in pairs and PAROE is high, PARI/O accepts a partial parity sum
from the first ALVCH16903.
A buffered output-enable (OE) input can be used to place the 24 outputs and
YERR in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components.
The ALVCH16903 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16903 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high-impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
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