IDT74ALVCH16901 Datasheet, PDF (1/9 Pages) Integrated Device Technology – 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS / CHECKERS AND BUS-HOLD

IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
IDT74ALVCH16901
UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/
CHECKERS AND BUS-HOLD
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity
transceiver with registers. The device can operate as a feed-through
transceiver or it can generate/check parity from the two 8-bit data buses in
either direction.
The ALVCH16901 features independent clock (CLKAB or CLKBA),
latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or
CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs
for checking parity. The direction of data flow is controlled by OEAB and
OEBA. When SEL is low, the parity functions are enabled. When SEL is high,
the parity functions are disabled and the device acts as an 18-bit registered
transceiver.
The ALVCH16901 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16901 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
LEAB ²
1CLKENAB 1
2
2CLKENAB 32
3
CLKAB
30
OEAB
35 _OEBA
1A1-1A8
1APAR ⁵
61
1ERRB
2A1-2A8
2APAR ²⁸
2ERRB ³⁶
ODD/EVEN ³⁴
SEL ³¹
A-Port
Parity
Generate
and
Check
B Data
18
18-Bit
18
Storage QA
18
18-Bit
18
QB ^Storage
B-Port
Parity
Generate
and
Check
A Data
2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©2000 Integrated Device Technology, Inc.
1B1-1B8
60 _1BPAR
4 _1ERRA
2B1-2A8
37
2BPAR
29
2ERRA
62 _CLKBA
64 1CLKENBA
33 _2CLKENBA
63 _LEBA
JUNE 2000
DSC-4582/1