IDT74ALVCH16721 Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD

IDT74ALVCH16721
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
3.3V CMOS 20-BIT
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16721
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Low switching noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 20-bit flip-flop is built using advanced dual metal CMOS technology. The
20 flip-flops of the ALVCH16721 are edge-triggered D-type flip-flops with
qualified clock storage. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs if the clock-enable (CLKEN) input
is low. If CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 20 outputs in either a normal
logic state (high or low) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly. The high-
impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect the internal
operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The ALVCH16721 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16721 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistor.
FUNCTIONAL BLOCK DIAGRAM
OE ¹
56
CLK
29
CLKEN
55
D1
CE
C1
1D
2
Q1
TO 19 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
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