IDT74ALVCH16374 Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS 16-BIT EDGE- TRIGGERED D-TYPE

IDT74ALVCH16374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE LATCH WITH 3-STATE OUTPUTS
3.3V CMOS 16-BIT EDGE-
TRIGGERED D-TYPE
LATCH WITH 3-STATE
OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16374
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal
CMOS technology. The ALVCH16374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can
be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of
the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the
data (D) inputs. OE can be used to place the eight outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The high-
impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal
operations of the flip-flop. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The ALVCH16374 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16374 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistor.
FUNCTIONAL BLOCK DIAGRAM
1OE ¹
2OE ²⁴
48
1CLK
2CLK ²⁵
C1
C1
2 _1Q1
13 _2Q1
1D1 ⁴⁷
1D
36
2D1
1D
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4564/1