IDT74ALVCH16345 Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD

IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS
3.3V CMOS REGISTERED
ADDRESS LINE DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16345
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
• High speed synchronous DRAM modules
• PC motherboards
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
This registered address line driver is built using advanced dual metal CMOS
technology. The ALVCH16345 is configured with banks of four drivers, each
to be used in high speed synchronous memory applications.
The ALVCH16345 is ideal for driving memory modules in systems where
multiple memory modules are used. One each of the four output banks drives
a different module; modules can be added or removed without affecting the signal
integrity of the other modules in the system. Dual clock enables (CEx) allow use
of the device in high speed memory interleaving applications where the clock
can be alternately enabled and disabled, allowing the address to be held for
additional cycles during memory access.
The ALVCH16345 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16345 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistors.
CE1
1
29
OE
D1
8
CE
D
1Q1
4Q1
CE2 ⁵⁶
D5
36
CE
D
1Q5
4Q5
14
D2
CE
D
1Q2
4Q2
42
D6
CE
D
1Q6
4Q6
D3
15
CE
D
1Q 3
4Q3
43
D7
CE
D
1Q 7
4Q7
21
D4
28
CLK
CE
D
1Q 4
4Q4
D8 ⁴⁹
CE
D
1Q 8
4Q8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4734/2