IDT74ALVCH162820 Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS 10-BIT FLIP FLOP WITH DUAL OUTPUTS

IDT74ALVCH162820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
3.3V CMOS 10-BIT FLIP-
FLOP WITH DUAL OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162820
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
This 10-bit flip-flop is built using advanced dual metal CMOS technology.
The ALVCH162820 is an edge-triggered D-type flip-flop. On the positive
transition of the clock (CLK) input, the device provides true data at the Q
outputs.
A buffered output-enable (OE) input can be used to place the ten outputs
in either a normal logic state (high or low logic level) or a high-impedance
state. In the high impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without the need for interface or pullup
components. OE input does not affect the internal operation of the flip-flops.
Old data can be retained or new data can be entered while the outputs are
in the high-impedance state.
The ALVCH162820 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCH162820 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
1
1OE
28
2OE
CLK
56
D1
55
C1
D1
2 _1Q1
3 _1Q2
TO NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
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