IDT74ALVCH16270 Datasheet, PDF (1/7 Pages) Integrated Device Technology – 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS AND BUS-HOLD

IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO
24-BIT REGISTERED BUS
EXCHANGER WITH 3-STATE
OUTPUTS AND BUS-HOLD
IDT74ALVCH16270
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This registered bus exchanger is built using advanced dual metal CMOS
technology. The ALVCH16270 is used in applications in which data must be
transferred from a narrow high-speed bus to a wide lower-frequency bus.
This device provides synchronous data exchange between the two ports.
Data is stored in the internal registers on the low-to-high transition of the clock
(CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The
select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the
A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single
storage register in the A-to-2B path. Proper control of the CLKENA input allows
two sequential 12-bit words to be presented synchronously as a 24-bit word on
the B-port. Data flow is controlled by the active-low output enables (OEA and
OEB). The control terminals are registered to synchronize the bus-direction
changes with CLK.
The ALVCH16270 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16270 has “bus-hold” which retains the inputs’ last state when-
ever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
CLK ²⁹
2
CLKEN1B
27
CLKEN2B
30
CLKENA1
CLKENA2 ⁵⁵
56
OEB
28
SEL
1
OEA
1D
C1
A1 ⁸
0
1
CE
C1
1D
1 of 12 Channels
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
23 _1B1
6
2B 1
AUGUST 1999
DSC-4475/1