IDT74ALVC125 Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

IDT74ALVC125
3.3V CMOS QUADRUPLE BUS BUFFER GATE
3.3V CMOS
QUADRUPLE BUS
BUFFER GATE WITH
3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC125
FEATURES:
– 0.5 MICRON CMOS Technology
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– VCC = 3.3V ± 0.3V, Normal Range
– VCC = 2.7V to 3.6V, Extended Range
– VCC = 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
– Available in SOIC, SSOP and TSSOP packages
Drive Features for ALVC125:
– High Output Drivers: ±24mA
– Suitable for heavy loads
DESCRIPTION:
This quadruple bus buffer gate is built using advanced dual metal CMOS
technology. The ALVC125 features independent line drivers with 3-state
outputs. Each output is disabled when the associated output-enable (OE)
input is high.
The ALVC125 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
1OE
1A ²
4
2OE
5
2A
3
1Y
6
2Y
10
3OE
9
3A
13
4OE
12
4A
8 _3Y
11
4Y
INDUSTRIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
SEPTEMBER 2000
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