IDT72V7230 Datasheet, PDF (1/42 Pages) Integrated Device Technology – 3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO
512 x 72, 1,024 x 72
2,048 x 72, 4,096 x 72
8,192 x 72, 16,384 x 72
32,768 x 72, 65,536 x 72
IDT72V7230, IDT72V7240
IDT72V7250, IDT72V7260
IDT72V7270, IDT72V7280
IDT72V7290, IDT72V72100
FEATURES:
• Choose among the following memory organizations:
IDT72V7230  512 x 72
IDT72V7240  1,024 x 72
IDT72V7250  2,048 x 72
IDT72V7260  4,096 x 72
IDT72V7270  8,192 x 72
IDT72V7280  16,384 x 72
IDT72V7290  32,768 x 72
IDT72V72100  65,536 x 72
• 100 MHz operation (10 ns read/write cycle time)
• User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
• Big-Endian/Little-Endian user selectable word representation
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
FUNCTIONAL BLOCK DIAGRAM
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Asynchronous operation of Output Enable, OE
• Read Chip Select ( RCS ) on Read Side
• Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
• Features JTAG (Boundary Scan)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
WEN _WCLK
D0 -Dn (x72, x36 or x18)
LD SEN SCLK
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
BE
IP
BM
IW
OW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
WRITE POINTER
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
JTAG
CONTROL
(BOUNDARY SCAN)
RAM ARRAY
512 x 72
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
OUTPUT REGISTER
OE
Q0 -Qn (x72, x36 or x18)
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
READ
RT
CONTROL
LOGIC
RM
RCLK
REN
RCS
4680 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DECEMBER 2003
DSC-4680/9