IDT72V71660 Datasheet, PDF (1/31 Pages) Integrated Device Technology – 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 X 16,384

3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
16,384 X 16,384
IDT72V71660
FEATURES:
• 16K x 16K non-blocking switching at 16.384Mb/s
• 64 serial input and output streams
• Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or
16.384Mb/s
• Per-channel Variable Delay Mode for low-latency applications
• Per-channel Constant Delay Mode for frame integrity applications
• Automatic identification of ST-BUS^® and GCI bus interfaces
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high-impedance output control
• Direct microprocessor access to all internal memories
• Memory block programming for quick setup
• IEEE-1149.1 (JTAG) Test Port
• 3.3V Power Supply
• Available in 208-pin (17mm x 17mm) Plastic Ball Grid Array
(PBGA) and 208-pin (28mm x 28mm) Plastic Quad Flatpack
(PQFP) packages
• Operating Temperature Range -40°C to +85°C
DESCRIPTION:
The IDT72V71660 has a non-blocking switch capacity of 2,048 x 2,048
channels at 2.048Mb/s, 4,096 x 4,096 channels at 4.096Mb/s, and 8,192 x
8,192 channels at 8.192Mb/s and 16,384 x 16,384 channels at 16.384Mb/s.
With 64 inputs and 64 outputs, programmable per stream control, and a variety
of operating modes the IDT72V71660 is designed for the TDM time slot
interchange function in either voice or data applications.
Some of the main features of the IDT72V71660 are LOW power 3.3 Volt
operation, automatic ST-BUS^® /GCI sensing, memory block programming,
simple microprocessor interface, one cycle direct internal memory accesses,
JTAG Test Access Port (TAP) and per stream programmable input offset delay,
variable or constant throughput modes, output enable and processor mode.
The IDT72V71660 is capable of switching up to 16,384 x 16,384 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per-channel basis.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
RESET
ODE
RX0
RX1
Receive
Serial Data
Streams
RX63
Timing Unit
TX0
Data Memory
MUX
TX1
Internal
Registers
Connection
Memory
Microprocessor Interface
Transmit
Serial Data
Streams
TX3
T1X32/OEI0
TX33/OEI1
JTAG Port
TX63/OEI31
CLK FP FE/HCLK WFPS
DS CS R/W A0-A15
DTA D0-D15
TMS TDI TCK TDO TRST
5905 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS^ is a trademark of Mitel Corp.
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 2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
JUNE 2004
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