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IDT72V70840_08 Datasheet, PDF (1/20 Pages) Integrated Device Technology – 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
4,096 x 4,096
IDT72V70840
.EATURES:
• 32 serial input and output streams
• 4,096 x 4,096 channel non-blocking switching at 8.192 Mb/s
• Accepts data streams at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
• Per-channel Variable Delay Mode for low-latency applications
• Per-channel Constant Delay Mode for frame integrity applica-
tions
• Automatic identification of ST-BUS® and GCI serial streams
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Per-channel processor mode to allow microprocessor writes to
TX streams
• Direct microprocessor access to all internal memories
• Memory block programming for quick set-up
• IEEE-1149.1 (JTAG) Test Port
• Internal Loopback for testing
• Available in 144-pin Thin Quad Flatpack (TQFP) and
144-pin Ball Grid Array (BGA) packages
• Operating Temperature Range -40°C to +85°C
• 3.3V I/O with 5V tolerant inputs and TTL compatible outputs
DESCRIPTION:
The IDT72V70840 has a non-blocking switch capacity of 1,024 x 1,024
channels at 2.048 Mb/s, 2,048 x 2,048 channels at 4.096 Mb/s, and 4,096 x
4,096 channels at 8.192 Mb/s. With 32 inputs and 32 outputs, programmable
per stream control, and a variety of operating modes the IDT72V70840 is
designed for the TDM time slot interchange function in either voice or data
applications.
Some of the main features of the IDT72V70840 are low power 3.3 Volt
operation, automatic ST-BUS®/GCI sensing, memory block programming,
simple microprocessor interface, one cycle direct internal memory accesses,
.UNCTIONAL BLOCK DIAGRAM
Vcc GND RESET
TMS TDI TDO TCK TRST
ODE
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
Receive
Serial Data
Streams
Timing Unit
Test Port
Loopback
Data Memory
Output
MUX
Transmit
Serial Data
Streams
Internal
Registers
Connection
Memory
Microprocessor Interface
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
TX16
TX17
TX18
TX19
TX20
TX21
TX22
TX23
TX24
TX25
TX26
TX27
TX28
TX29
TX30
TX31
CLK F0i FE/ WFPS DS CS R/W A0-A13 DTA D0-D15
HCLK
5715 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
1
 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
October 2008
DSC-5715/4