IDT72V291 Datasheet, PDF (1/26 Pages) Integrated Device Technology – 3.3 VOLT CMOS SuperSync FIFOTM

3.3 VOLT CMOS SuperSync FIFO™
65,536 x 9
131,072 x 9
IDT72V281
IDT72V291
.EATURES:
• Choose among the following memory organizations:
IDT72V281
65,536 x 9
IDT72V291
131,072 x 9
• Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin
Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial Temperature Range (-40°C to + 85°C) is available
DESCRIPTION:
The IDT72V281/72V291 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
.UNCTIONAL BLOCK DIAGRAM
WEN _WCLK
D0-D8
LD SEN
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
65,536 x 9
131,072 x 9
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
MRS
PRS
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
RT
LOGIC
RCLK
REN
Q0-Q8
OE
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
 2001 Integrated Device Technology, Inc.
4513 drw 01
APRIL 2001
DSC-4513/1