IDT72V275_14 Datasheet, PDF (1/25 Pages) Integrated Device Technology – 3.3 VOLT CMOS SuperSync FIFO

3.3 VOLT CMOS SuperSync FIFO™
32,768 x 18
65,536 x 18
IDT72V275
IDT72V285
FEATURES:
• Choose among the following memory organizations:
IDT72V275
32,768 x 18
IDT72V285
65,536 x 18
• Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin
FUNCTIONAL BLOCK DIAGRAM
WEN _WCLK
D0 -D17
Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
• Green parts are available, see ordering information
DESCRIPTION:
The IDT72V275/72V285 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
• The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs, RCLK
or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to
an empty FIFO to the time it can be read, is now fixed and short. (The
variable clock cycle counting delay associated with the latency period
found on previous SuperSync devices has been eliminated on this
SuperSync family.)
SuperSync FIFOs are particularly appropriate for network, video, telecom-
munications, data communications and other applications that need to buffer
large amounts of data.
LD SEN
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
32,768 x 18
65,536 x 18
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
MRS
PRS
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
RT
LOGIC
RCLK
REN
Q0 -Q17
OE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
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