IDT72V223 Datasheet, PDF (1/45 Pages) Integrated Device Technology – 3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO

3.3 VOLT HIGH-DENSITY SUPERSYNC II™
NARROW BUS FIFO
512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9
IDT72V223, IDT72V233
IDT72V243, IDT72V253
IDT72V263, IDT72V273
IDT72V283, IDT72V293
FEATURES:
• Choose among the following memory organizations:
IDT72V223  512 x 18/1,024 x 9
IDT72V233  1,024 x 18/2,048 x 9
IDT72V243  2,048 x 18/4,096 x 9
IDT72V253  4,096 x 18/8,192 x 9
IDT72V263  8,192 x 18/16,384 x 9
IDT72V273  16,384 x 18/32,768 x 9
IDT72V283  32,768 x 18/65,536 x 9
IDT72V293  65,536 x 18/131,072 x 9
• Functionally compatible with the IDT72V255LA/72V265LA and
IDT72V275/72V285 SuperSync FIFOs
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (BGA Only)
• User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
• Pin to Pin compatible to the higher density of IDT72V2103/72V2113
• Big-Endian/Little-Endian user selectable byte representation
• 5V tolerant inputs
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (BGA Only)
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball
Grid Array (BGA) (with additional features)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
*Available on the
BGA package only.
* ^{WEN WCLK/WR}
D0 -Dn (x9 or x18)
LD SEN
INPUT REGISTER
OFFSET REGISTER
*^ASYW
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
512 x 18 or 1,024 x 9
1,024 x 18 or 2,048 x 9
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
BE
CONTROL
IP
LOGIC
IW
BUS
OW
CONFIGURATION
OUTPUT REGISTER
READ
CONTROL
LOGIC
MRS
PRS
RESET
LOGIC
TCK
*_TRST
* _TMS
* _TDI
**^TDO
*
JTAG CONTROL
(BOUNDARY SCAN)
OE
Q0 -Qn (x9 or x18)
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RT
RM
* ^ASYR
* ^RCLK/RD
REN
4666 drw01
SEPTEMBER 2003
DSC-4666/12