IDT72V01 Datasheet, PDF (1/13 Pages) Integrated Device Technology – 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9

Integrated Device Technology, Inc.
3.3 VOLT CMOS
ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
IDT72V01
IDT72V02
IDT72V03
IDT72V04
FEATURES:
• 3.3V family uses 70% less power than the 5 Volt 7201/
02/03/04 family
• 512 x 9 organization (72V01)
• 1024 x 9 organization (72V02)
• 2048 x 9 organization (72V03)
• 4096 X 9 organization (72V04)
• Functionally compatible with 720x family
• 25 ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• Available in 32-pin PLCC and 28-pin SOIC Package (to
be determined)
• Industrial temperature range (-40^oC to +85^oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72V01/72V02/72V03/72V04 are dual-port FIFO
memories that operate at a power supply voltage (Vcc)
between 3.0V and 3.6V. Their architecture, functional opera-
tion and pin assignments are identical to those of the IDT7201/
7202/7203/7204. These devices load and empty data on a
first-in/first-out basis. They use Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
W R through the use of the Write ( ) and Read ( ) pins. The devices
have a maximum data access time as fast as 25 ns.
The devices utilize a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
RT error checking. They also feature a Retransmit ( ) capability
that allows for reset of the read pointer to its initial position
RT when is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
The IDT72V01/72V02/72V03/72V04 is fabricated using
IDT’s high-speed CMOS technology. It has been designed for
those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
W
WRITE
CONTROL
DATA INPUTS
(D 0 –D 8)
WRITE
POINTER
RAM
ARRAY
512x 9
1024 x 9
2048 x 9
4096 x 9
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q 0–Q8)
RS
RESET
LOGIC
FLAG
LOGIC
EF
FL/RT
FF
EXPANSION
XI
LOGIC
XO/HF
2679 drw 01
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.08
DECEMBER 1996
DSC-3033/6
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