IDT72T54242 Datasheet, PDF (1/56 Pages) Integrated Device Technology – 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS

2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO
x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
32,768 x 10 x 4/16,384 x 20 x 2
65,536 x 10 x 4/32,768 x 20 x 2
131,072 x 10 x 4/65,536 x 20 x 2
IDT72T54242
IDT72T54252
IDT72T54262
FEATURES
• Choose from among the following memory organizations:
IDT72T54242 - 32,768 x 10 x 4/32,768 x 10 x 2
IDT72T54252 - 65,536 x 10 x 4/65,536 x 10 x 2
IDT72T54262 - 131,072 x 10 x 4/131,072 x 10 x 2
• User Selectable Quad / Dual Mode - Choose between two or
four independent FIFOs
• Quad Mode offers
- Eight discrete clock domain, (four write clocks & four read clocks)
- Four separate write ports, write data to four independent FIFOs
- 10-bit wide write ports
- Four separate read ports, read data from any of four independent FIFOs
- Independent set of status flags and control signals for each FIFO
• Dual Mode offers
- Four discrete clock domain, (two write clocks & two read clocks)
- Two separate write ports, write data to two independent FIFOs
- 10-bit/20-bit wide write ports
- Two separate read ports, read data from any of two independent FIFOs
- Independent set of status flags and control signals for each FIFO
- Bus-Matching on read and write port x10/x20
- Maximum depth of each FIFO is the same as in Quad Mode
• Up to 200MHz operating frequency or 2Gbps throughput in SDR mode
• Up to 100MHz operating frequency or 2Gbps throughput in DDR mode
• Double Data Rate, DDR is selectable, providing up to 400Mbps
bandwidth per data pin
• User selectable Single or Double Data Rate modes on both the
write port(s) and read port(s)
• All I/Os are LVTTL/ HSTL/ eHSTL user selectable
• 3.3V tolerant inputs in LVTTL mode
• ERCLK and EREN Echo outputs on all read ports
• Write enable WEN and Chip Select WCS input for each write port
• Read enable REN and Chip Select RCS input for each read port
• User Selectable IDT Standard mode (using EF and FF) or FWFT
mode (using IR and OR)
• Programmable Almost Empty and Almost Full flags per FIFO
• Dedicated Serial Port for flag offset programming
• Power Down pin minimizes power consumption
• 2.5V Supply Voltage
• Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm
• IEEE 1149.1 compliant JTAG port provides boundary scan function
• Low Power, High Performance CMOS technology
• Industrial temperature range (-40°C to +85°C)
FUNCTIONAL BLOCK DIAGRAMS
Quad Mode
FIFO 0
WCLK0
WEN0
WCS0
Data In D[9:0] _x10
FIFO 1
WCLK1
WEN1
WCS1
Data In D[19:10] _x10
FIFO 2
WCLK2
WEN2
WCS2
Data In D[29:20] _x10
WCLK3
WEN3
FIFO 3 WCS3
Data In D[39:30] _x10
32,768 x 10
65,536 x 10
131,072 x 10
FIFO 0
32,768 x 10
65,536 x 10
131,072 x 10
FIFO 1
32,768 x 10
65,536 x 10
131,072 x 10
FIFO 2
32,768 x 10
65,536 x 10
131,072 x 10
RCLK0
REN0
RCS0
OE0
ERCLK0
EREN0
FIFO 0
x10
Q[9:0] ^{Data Out}
RCLK1
REN1
RCS1
OE1
ERCLK1
EREN1
FIFO 1
x10
Q[19:10] ^{Data Out}
RCLK2
REN2
RCS2
OE2
ERCLK2
EREN2
FIFO 2
x10
Q[29:20] ^{Data Out}
RCLK3
REN3
RCS3
OE3
ERCLK3
EREN3
FIFO 3
Data Out
x10 _Q[39:30]
FIFO 3
FF0/IR0
PAF0
FF1/IR1
PAF1
FF2/ IR2
PAF2
FF3/IR3
PAF3
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IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
EF0/OR0
PAE0
EF1/OR1
PAE1
EF2/OR2
PAE2
EF3/OR3
PAE3
(See next page for Dual Mode)
MARCH 2005
1
 _{2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.}
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