IDT728985 Datasheet, PDF (1/13 Pages) Integrated Device Technology – TIME SLOT INTERCHANGE DIGITAL SWITCH

TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
IDT728985
.EATURES:
• 256 x 256 channel non-blocking switch
• Automatic signal identification (ST-BUS^®, GCI)
• 8 RX inputs — 32 channels at 64 Kbit/s per serial line
• 8 TX outputs — 32 channels at 64 Kbit/s per serial line
• Three-state serial outputs
• Microprocessor Interface (8-bit data bus)
• Frame Integrity for data applications
• 5V Power Supply
• Operating Temperature Range -40°C to +85°C
• Available in 44-pin Plastic Leaded Chip Carrier (PLCC),
44-pin Plastic Quad Flatpack (PQFP) and 40-pin Plastic Dip
(P-DIP)
DESCRIPTION:
The IDT728985 is a ST-BUS^®/GCI compatible digital switch controlled by
a microprocessor. The IDT728985 can handle as many as 256, 64 Kbit/s input
and output channels. Those 256 channels are divided into 8 serial inputs and
outputs, each of which consists of 32 channels. The IDT728985 provides per-
channel variable or constant throughput delay modes and microprocessor read
and write access to individual channels. As an important function of a digital
switch is to maintain sequence integrity and minimize throughput delay, the
IDT728985 is an ideal solution for most switching needs.
.UNCTIONAL DESCRIPTION
Frame sequence, constant throughput delay, and guaranteed minimum
delay are high priority requirements in today’s integrated data and multimedia
networks. The IDT728985 provides these functions on a per-channel basis
using a standard microprocessor control interface. Each of the eight serial lines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
In Processor Mode, the microprocessor can access the input and output time
slots to control other devices such as ISDN transceivers and trunk interfaces.
Supporting both GCI and ST-BUS^® formats, IDT728985 has incorporated an
internal circuit to automatically identify the polarity and format of the frame
synchronization.
A functional block diagram of the IDT728985 device is shown on page 1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and
.UNCTIONAL BLOCK DIAGRAM
C4i F0i VCC GND
ODE
RX0
Timing
TX0
RX1
Unit
Output MUX
TX1
RX2
Receive
RX3
Serial Data
Data
RX4
Streams
Memory
TX2
Transmit
Serial Data
TX3
Streams
TX4
RX5
Control Register
Connection
TX5
RX6
Memory
TX6
RX7
Microprocessor Interface
TX7
DS CS R/W A0/ _DTA D0/
A5
D7
CCO
5708 drw01
1
2001 Integrated Device Technology, Inc.
APRIL 2001
DSC-5708/2