IDT72605_13 Datasheet, PDF (1/17 Pages) Integrated Device Technology – CMOS SyncBiFIFOTM

CMOS SyncBiFIFO^TM
256 x 18 x 2
512 x 18 x 2
IDT72605
IDT72615
FEATURES:
• Two independent FIFO memories for fully bidirectional data
transfers
• 256 x 18 x 2 organization (IDT72605)
• 512 x 18 x 2 organization (IDT72615)
• Synchronous interface for fast (20ns) read and write cycle times
• Each data port has an independent clock and read/write control
• Output enable is provided on each port as a three-state control
of the data bus
• Built-in bypass path for direct data transfer between two ports
• Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO
• Programmable flag offset can be set to any depth in the FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin
Quad Flatpack) and 68-pin PLCC
• Industrial temperature range (–40°C to +85°C)
• Green parts available, see ordering information
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-power bidirec-
tional First-In, First-Out (FIFO) memories, with synchronous interface for fast
read and write cycle times. The SyncBiFIFO™ is a data buffer that can store
or retrieve information from two sources simultaneously. Two Dual-Port FIFO
memory arrays are contained in the SyncBiFIFO; one data buffer for each
direction.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Each Port has its own independent clock. Data transfers to the
I/O registers are gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individual output enable
signals control whether the SyncBiFIFO is driving the data lines of a port or
whether those data lines are in a high-impedance state.
Bypass control allows data to be directly transferred from input to output
register in either direction.
The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full,
and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full
and Almost-Empty flags can be programmed to any location.
The SyncBiFIFO is fabricated using high-speed, submicron CMOS tech-
nology.
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
ENA
R/WA
OEA
HIGH
Z
CONTROL
CSA
A2
A1
A0
EFAB
PAEAB
PAFAB
FFAB
CLKA
μP
INTERFACE
FLAG
LOGIC
INPUT REGISTER
MEMORY
ARRAY
512 x 18
256 x 18
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
CLKB
MUX
OUTPUT REGISTER
INPUT REGISTER
OEB
R/WB
ENB
HIGH
Z
CONTROL
BYPB
DB0-DB17
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RESET
LOGIC
FLAG
LOGIC
POWER
SUPPLY
RS
EFBA
PAEBA
PAFBA
FFBA
3 _VCC
7 _GND
2704 drw 01
FEBRUARY 2013
DSC-2704/10