IDT72605 Datasheet, PDF (1/20 Pages) Integrated Device Technology – CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2

CMOS SyncBiFIFO^™
256 x 18 x 2 and 512 x 18 x 2
IDT72605
IDT72615
Integrated Device Technology, Inc.
FEATURES:
• Two independent FIFO memories for fully bidirectional
data transfers
• 256 x 18 x 2 organization (IDT 72605)
• 512 x 18 x 2 organization (IDT 72615)
• Synchronous interface for fast (20ns) read and write
cycle times
• Each data port has an independent clock and read/write
control
• Output enable is provided on each port as a three-state
control of the data bus
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP
(Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-
power bidirectional First-In, First-Out (FIFO) memories, with
synchronous interface for fast read and write cycle times. The
SyncBiFIFO™ is a data buffer that can store or retrieve
information from two sources simultaneously. Two Dual-Port
FIFO memory arrays are contained in the SyncBiFIFO; one
data buffer for each direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individ-
ual output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines are
in a high-impedance state.
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memo-
ries. The offset depths of the almost-full and almost-empty
flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT’s high-speed,
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
ENA
R/WA
OEA
HIGH
Z
CONTROL
CSA
A2
A1
A0
EFAB
PPAAEFAABB
FFAB
CLKA
µP
INTERFACE
FLAG
LOGIC
CLKB
INPUT REGISTER
MEMORY
ARRAY
512 x 18
256 x 18
MUX
OUTPUT REGISTER
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
INPUT REGISTER
RESET
LOGIC
FLAG
LOGIC
POWER
SUPPLY
RS
EPPFFAAF_BBFEAABBAA
3
VCC
7 _GND
OEB
R/WB
ENB
HIGH
Z
CONTROL
BYPB
DB0-DB17
SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
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DECEMBER 1996
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