IDT72510 Datasheet, PDF (1/32 Pages) Integrated Device Technology – BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT

Integrated Device Technology, Inc.
BUS-MATCHING
BIDIRECTIONAL FIFO
512 x 18-BIT – 1024 x 9-BIT
1024 x 18-BIT – 2048 x 9-BIT
IDT72510
IDT72520
FEATURES:
• Two side-by-side FIFO memory arrays for bidirectional
data transfers
• 512 x 18-Bit – 1024 x 9-Bit (IDT72510)
• 1024 x 18-Bit – 2048 x 9-Bit (IDT72520)
• 18-bit data bus on Port A side and 9-bit data bus on Port
B side
• Can be configured for 18-to-9-bit, 36-to-9-bit, or 36-to-18-
bit communication
• Fast 25ns access time
• Fully programmable standard microprocessor interface
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Two programmable flags, Almost-Empty and Almost-Full
for each FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• Any of the eight internal flags can be assigned to four
external flag pins
• Flexible reread/rewrite capabilities.
• On-chip parity checking and generation
• Standard DMA control pins for data exchange with
peripherals
• IDT72510 and IDT72520 available in the the 52-pin PLCC
package
DESCRIPTION:
The IDT72510 and IDT72520 are highly integrated first-
in, first-out memories that enhance processor-to-processor
and processor-to-peripheral communications. IDT BiFIFOs
integrate two side-by-side memory arrays for data transfers
in two directions.
The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. The BiFIFOs
incorporate bus matching logic to convert the 18-bit wide
memory data paths to the 9-bit wide Port B data bus. The
BiFIFOs have a bypass path that allows the device con-
nected to Port A to pass messages directly to the Port B
device.
Ten registers are accessible through Port A, a
Command Register, a Status Register, and eight Configuration
Registers.
The IDT BiFIFOs have programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight inter-
nal flags can be assigned to any of four external flag pins
(FLGA-FLGD) through one Configuration Register.
Port B has parity, reread/rewrite and DMA functions. Par-
ity generation and checking can be done by the BiFIFO on
data passing through Port B. The Reread and Rewrite con-
SIMPLIFIED BLOCK DIAGRAM
18-Bit
FIFO
18-bits
Data
Bypass Path
9-bits
9-bits
Data
Port
A
18-Bit
FIFO
Port
B
Control
Processor
Interface
A
Registers
Processor
Interface
B
Flags
Programmable
Flag Logic
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.31
Handshake
Interface
Control
DMA
2669 drw 01
DECEMBER 1995
DSC-2669/-
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