IDT72413 Datasheet, PDF (1/11 Pages) Integrated Device Technology – CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

Integrated Device Technology, Inc.
CMOS PARALLEL
64 x 5-BIT FIFO
WITH FLAGS
IDT72413
FEATURES:
• First-ln/First-Out Dual-Port memory—45MHz
• 64 x 5 organization
• Low-power consumption
— Active: 200mW (typical)
• RAM-based internal structure allows for fast fall-through
time
• Asynchronous and simultaneous read and write
• Expandable by bit width
• Cascadable by word depth
• Half-Full and Almost-Full/Empty status flags
• IDT72413 is pin and functionally compatible with the
MMI67413
• High-speed data communications applications
• Bidirectional and rate buffer applications
• High-performance CMOS technology
• Available in plastic DIP, CERDIP and SOIC
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40^oC to +85^oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72413 is a 64 x 5, high-speed First-In/First-Out
(FIFO) that loads and empties data on a first-in-first-out basis.
It is expandable in bit width. All speed versions are cascad-
able in depth.
The FIFO has a Half-Full Flag, which signals when it has 32
or more words in memory. The Almost-Full/Empty Flag is
active when there are 56 or more words in memory or when
there are 8 or less words in memory.
The IDT72413 is pin and functionally compatible to the
MMI67413. It operates at a shift rate of 45MHz. This makes it
ideal for use in high-speed data buffering applications. The
IDT72413 can be used as a rate buffer, between two digital
systems of varying data rates, in high-speed tape drivers, hard
disk controllers, data communications controllers and
graphics controllers.
The IDT72413 is fabricated using IDTs high-performance
CMOS process. This process maintains the speed and high
output drive capability of TTL circuits in low-power CMOS.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
OUPUT ENABLE
(OE)
DATAIN
(D0-4 )
FIFO
INPUT
STAGE
(MR)
MASTER
RESET
INPUT ^(IR)
READY
SHIFT
IN _(SI)
INPUT
CONTROL
LOGIC
64 x 5
MEMORY
ARRAY
REGISTER
CONTROL
LOGIC
FLAG
CONTROL
LOGIC
FIFO
OUTPUT
STAGE
DATA OUT
(Q0-4 )
OUTPUT
CONTROL
LOGIC
(SO)
(OR)
SHIFT
OUT
OUPUT
READY
HALF-FULL (HF)
ALMOST-FULL/
EMPTY (AF/E)
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The IDT logo is a registered trademark of Integrated Device Technology,Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.02
DECEMBER 1996
DSC-2748/7
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