IDT72401 Datasheet, PDF (1/9 Pages) Integrated Device Technology – CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT

Integrated Device Technology, Inc.
CMOS PARALLEL FIFO
64 x 4-BIT AND 64 x 5-BIT
IDT72401
IDT72402
IDT72403
IDT72404
FEATURES:
• First-ln/First-Out Dual-Port memory
• 64 x 4 organization (IDT72401/03)
• 64 x 5 organization (IDT72402/04)
• IDT72401/02 pin and functionally compatible with
MMI67401/02
• RAM-based FIFO with low falI-through time
• Low-power consumption
— Active: 175mW (typ.)
• Maximum shift rate — 45MHz
• High data output drive capability
• Asynchronous and simultaneous read and write
• Fully expandable by bit width
• Fully expandable by word depth
• IDT72403/04 have Output Enable pin to enable output
data
• High-speed data communications applications
• High-performance CMOS technology
• Available in CERDIP, plastic DIP and SOIC
• Military product compliant to MlL-STD-883, Class B
• Standard Military Drawing #5962-86846 and
5962-89523 is listed on this function.
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous high-
performance First-ln/First-Out memories organized 64 words
by 4 bits. The IDT72402 and IDT72404 are asynchronous
high-performance First-ln/First-Out memories organized as
64 words by 5 bits. The IDT72403 and IDT72404 also have an
Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data
at the data input (D0-D3, 4). The stored data stack up on a first-
in/first-out basis.
A Shift Out (SO) signal causes the data at the next to last
word to be shifted to the output while all other data shifts down
one location in the stack. The Input Ready (IR) signal acts like
a flag to indicate when the input is ready for new data
(IR = HIGH) or to signal when the FIFO is full (IR = LOW). The
Input Ready signal can also be used to cascade multiple
devices together. The Output Ready (OR) signal is a flag to
indicate that the output remains valid data (OR = HIGH) or to
indicate that the FIFO is empty (OR = LOW). The Output
Ready can also be used to cascade multiple devices together.
Width expansion is accomplished by logically ANDing the
Input Ready (IR) and Output Ready (OR) signals to form
composite signals.
Depth expansion is accomplished by tying the data inputs
of one device to the data outputs of the previous device. The
Input Ready pin of the receiving device is connected to the
Shift Out pin of the sending device and the Output Ready pin
of the sending device is connected to the Shift In pin of the
receiving device.
Reading and writing operations are completely asynchro-
nous allowing the FIFO to be used as a buffer between two
digital machines of widely varying operating frequencies. The
45MHz speed makes these FlFOs ideal for high-speed
communication and controller applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
SI
INPUT
CONTROL
IR
LOGIC
D 0-3
D4
(IDT72402
and IDT72404)
MR
DATA IN
MASTER
RESET
WRITE POINTER
WRITE MULTIPLEXER
MEMORY
ARRAY
READ MULTIPLEXER
READ POINTER
OUTPUT
ENABLE
DATA OUT
OUTPUT
CONTROL
LOGIC
OE (IDT72403 and
IDT72404)
Q 0-3
Q 4 (IDT72402 and
IDT72404)
SO
OR
2747 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.01
SEPTEMBER 1996
DSC-2747/7
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