IDT72255LA_05 Datasheet, PDF (1/27 Pages) Integrated Device Technology – CMOS SuperSync FIFO

CMOS SuperSync FIFO^™
8,192 x 18
16,384 x 18
IDT72255LA
IDT72265LA
FEATURES
• Choose among the following memory organizations:
IDT72255LA — 8,192 x 18
IDT72265LA — 16,384 x 18
• Pin-compatible with the IDT72275/72285 SuperSync FIFOs
• 10ns read/write cycle time (8ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
FUNCTIONAL BLOCK DIAGRAM
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
DESCRIPTION
The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls. These
FIFOs offer numerous improvements over previous SuperSync FIFOs,
including the following:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
WEN WCLK
D0 -D17
L D SEN
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
8,192 x 18
16,384 x 18
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
F F /IR
PAF
EF /OR
PAE
HF
FWFT/SI
MRS
P RS
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
RT
LOGIC
RCLK
REN
Q0 -Q17
OE
4670 drw01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SuperSync FIFO is a trademark of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
 2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2005
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