IDT72132 Datasheet, PDF (1/13 Pages) Integrated Device Technology – CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9

Integrated Device Technology, Inc.
CMOS SERIAL-TO-PARALLEL FIFO
2048 x 9
4096 x 9
IDT72132
IDT72142
FEATURES:
• 35ns parallel-port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 8, 9, 16-18, and
32-36 bit using Flexshift™ serial input without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-Port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low-power CMOS
technology
• Available in the 28-pin plastic DIP
• Industrial temperature range (-40^oC to +85^oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72132/72142 are high-speed, low-power serial-to-
parallel FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). The IDT72132/72142 can be config-
ured with the IDTs parallel-to-serial FIFOs (IDT72131/72141)
for bidirectional serial data buffering.
The FIFO has a serial input port and a 9-bit parallel output
port. Wider and deeper serial-to-parallel data buffers can be
NW ^{built using multiple IDT72132/72142 chips. IDTs unique}
Flexshift serial expansion logic (SIX, ) makes width
expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16,
and 32 bits. The IDT72132/142 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The Almost-Full (7/8), Half-Full, and Almost Empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72132/72142 is fabricated using IDTs high-speed
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
SICP
SIX
SI
D7 D8
SERIAL INPUT
CIRCUITRY
NW
NEXT WRITE
POINTER
RAM ARRAY
2048 x 9
4096 x 9
RS
FL/RT
RESET
LOGIC
XI
EXPANSION
LOGIC
XO/ OE Q0-Q 8
PIN CONFIGURATION
FLAG
LOGIC
READ
POINTER
NW
1
GND
2
EF
XI
3
AEF
AEF
4
/HF
FF
FF
5
Q0
6
Q1
7
R
Q2
8
Q3
9
Q4
10
GND
11
R
12
Q5
13
Q6
14
P28-1
&
C28-3
28
Vcc
27
D7
26
D8
25
FL/RT
24
RS
23
SI
22
SICP
21
SIX
20
OE
19
EF
18
XO/HF
17
GND
16
Q8
15
Q7
2752 drw 01
DIP
TOP VIEW
2752 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.36
DECEMBER 1996
DSC-2752/6
1