IDT71V67803 Datasheet, PDF (1/23 Pages) Integrated Device Technology – 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect

256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
IDT71V67603
IDT71V67803
Features
x _{256K x 36, 512K x 18 memory configurations}
x _{Supports high system speed:}
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
x _{LBO input selects interleaved or linear burst mode}
x _{Self-timed write cycle with global write control (GW), byte}
write enable (BWE), and byte writes (BWx)
x _{3.3V core power supply}
x _{Power down controlled by ZZ input}
x _{3.3V I/O supply (VDDQ)}
x _{Packaged in a JEDEC Standard 100-pin thin plastic quad}
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V67603/7803 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67603/7803 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
CE
Chip Enable
CS0, CS1
Chip Selects
OE
Output Enable
GW
Global Write Enable
BWE
Byte Write Enable
BW1, BW2, BW3, BW4⁽¹⁾
Individual Byte Write Selects
CLK
Clock
ADV
Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS
Ground
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5310 tbl 01
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©2004 Integrated Device Technology, Inc.
SEPTEMBER 2004
DSC-5310/06