IDT71V67702 Datasheet, PDF (1/23 Pages) Integrated Device Technology – 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect

256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
IDT71V67702
IDT71V67902
Flow-Through Outputs, Single Cycle Deselect
Features
x _{256K x 36, 512K x 18 memory configurations}
x _{Supports fast access times:}
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
x _{LBO input selects interleaved or linear burst mode}
x _{Self-timed write cycle with global write control (GW), byte write}
enable (BWE), and byte writes (BWx)
x _{3.3V core power supply}
x _{Power down controlled by ZZ input}
x _{2.5V I/O supply (VDDQ)}
x _{Packaged in a JEDEC Standard 100-pin thin plastic quad}
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA).
Description
The IDT71V67702/7902 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67702/7902 SRAMs contain write,
data, address and control registers. There are no registers in the data
output path (flow-through architecture). Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67702/7902 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V67702/7902 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
CE
Chip Enable
CS0, CS1
Chip Selects
OE
Output Enable
GW
Global Write Enable
BWE
Byte Write Enable
BW1, BW2, BW3, BW4⁽¹⁾
Individual Byte Write Selects
CLK
Clock
ADV
Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS
Gro und
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67902.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5317 tbl 01
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©2002 Integrated Device Technology, Inc.
DECEMBER 2003
DSC-5317/08