IDT71V65603_08 Datasheet, PDF (1/26 Pages) Integrated Device Technology – 3.3V Synchronous ZBT SRAMs

256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
3.3V I/O, Burst Counter
Pipelined Outputs
IDT71V65603/Z
IDT71V65803/Z
Features
◆ _{256K x 36, 512K x 18 memory configurations}
◆ _{Supports high performance system speed - 150MHz}
(3.8ns Clock-to-Data Access)
◆ _ZBTTM _{Feature - No dead cycles between write and read cycles}
◆ _{Internally synchronized output buffer enable eliminates the}
need to control OE
◆ _{Single R/W (READ/WRITE) control pin}
◆ _{Positive clock-edge triggered address, data, and control signal}
registers for fully pipelined applications
◆ _{4-word burst capability (interleaved or linear)}
◆ _{Individual byte write (BW1 - BW4) control (May tie active)}
◆ _{Three chip enables for simple depth expansion}
◆ _{3.3V power supply (±5%)}
◆ _{3.3V I/O Supply (VDDQ)}
◆ _{Power down controlled by ZZ input}
◆ _{Packaged in a JEDEC standard 100-pin plastic thin quad}
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).
Description
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT^TM, or Zero Bus Turn-
around.
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read or write.
The IDT71V65603/5803 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803
to be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
The IDT71V65603/5803 have an on-chip burst counter. In the burst
mode, the IDT71V65603/5803 can provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the LBO input pin. The LBO pin selects
between linear and interleaved burst sequence. The ADV/LD signal is
used to load a new external address (ADV/LD = LOW) or increment
the internal burst counter (ADV/LD = HIGH).
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA) .
Pin Description Summary
A0-A18
Address Inputs
CE1, CE2, CE2
Chip Enables
OE
Output Enable
R/W
Read/Write Signal
CEN
Clock Enable
BW1, BW2, BW3, BW4
Individual Byte Write Selects
CLK
Clock
ADV/LD
Advance burst address / Load new address
LBO
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Asynchronous
Synchronous
Static
Static
5304 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
1
©2008 Integrated Device Technology, Inc.
OCTOBER 2008
DSC-5304/08