IDT71V632 Datasheet, PDF (1/19 Pages) Integrated Device Technology – 64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

64K x 32
3.3V Synchronous SRAM
Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V632
Features
x _{64K x 32 memory configuration}
x _{Supports high system speed:}
Commercial:
– A4 4.5ns clock access time (117 MHz)
Commercial and Industrial:
– 5 5ns clock access time (100 MHz)
– 6 6ns clock access time (83 MHz)
– 7 7ns clock access time (66 MHz)
x _{Single-cycle deselect functionality (Compatible with}
Micron Part # MT58LC64K32D7LG-XX)
x _{LBO input selects interleaved or linear burst mode}
x _{Self-timed write cycle with global write control (GW), byte}
write enable (BWE), and byte writes (BWx)
x _{Power down controlled by ZZ input}
x _{Operates with a single 3.3V power supply (+10/-5%)}
x _{Packaged in a JEDEC Standard 100-pin rectangular plastic}
thin quad flatpack (TQFP).
Description
The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32
with full support of the Pentium™ and PowerPC™ processor interfaces.
The pipelined burst architecture provides cost-effective 3-1-1-1 second-
ary cache performance for processors up to 117MHz.
The IDT71V632 SRAM contains write, data, address, and control
registers. Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the extreme end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V632 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address counter
accepts the first cycle address from the processor, initiating the access
sequence. The first cycle of output data will be pipelined for one cycle before
it is available on the next rising clock edge. If burst mode operation is
selected (ADV=LOW), the subsequent three cycles of output data will be
available to the user on the next three rising clock edges. The order of these
three addresses will be defined by the internal burst counter and the LBO
input pin.
The IDT71V632 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density
in both desktop and notebook applications.
Pin Description Summary
A0–A15
Address Inputs
CE
Chip Enable
CS0, CS1
Chips Selects
OE
Output Enable
GW
Global Write Enable
BWE
Byte Write Enable
BW1, BW2, BW3, BW4
Individual Byte Write Selects
CLK
Clock
ADV
Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O0–I/O31
Data Input/Output
VDD, VDDQ
3.3V
VSS, VSSQ
Array Ground, I/O Ground
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
1
©2000 Integrated Device Technology, Inc.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Power
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
3619 tbl 01
AUGUST 2001
DSC-3619/04