IDT71V547S Datasheet, PDF (1/20 Pages) Integrated Device Technology – Synchronous SRAM

128K X 36, 3.3V Synchronous IDT71V547S/XS
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
Features
◆ _{128K x 36 memory configuration, flow-through outputs}
◆ _{Supports high performance system speed - 95 MHz}
(8ns Clock-to-Data Access)
◆ _ZBTTM _{Feature - No dead cycles between write and read}
cycles
◆ _{Internally synchronized signal eliminates the need to}
control OE
Functional Block Diagram
LBO
Address A [0:16]
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
DQ
DQ
◆ _{Single R/W (READ/WRITE) control pin}
◆ _{4-word burst capability (Interleaved or linear)}
◆ _{Individual byte write (BW1 - BW4) control (May tie active)}
◆ _{Three chip enables for simple depth expansion}
◆ _{Single 3.3V power supply (±5%)}
◆ _{Packaged in a JEDEC standard 100-pin TQFP package}
128K x 36 BIT
MEMORY ARRAY
Address
Control
DI DO
DQ
Clk
Control Logic
Clock
Mux
Sel
OE
Gate
,
Data I/O [0:31], I/O P[1:4]
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
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©2015 Integrated Device Technology, Inc.
3822 drw 01
FEBRUARY 2015
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