IDT71V433 Datasheet, PDF (1/19 Pages) Integrated Device Technology – 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs

32K x 32
3.3V Synchronous SRAM
Flow-Through Outputs
IDT71V433
Features
x _{32K x 32 memory configuration}
x _{Supports high performance system speed:}
Commercial and Industrial:
— 11 11ns Clock-to-Data Access (50MHz)
— 12 12ns Clock-to-Data Access (50MHz)
x _{LBO input selects interleaved or linear burst mode}
x _{Self-timed write cycle with global write control (GW), byte}
write enable (BWE), and byte writes (BWx)
x _{Power down controlled by ZZ input}
x _{Single 3.3V power supply (+10/-5%)}
x _{Packaged in a JEDEC Standard 100-pin rectangular plastic}
thin quad flatpack (TQFP).
Description
The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAM orga-
nized as 32K x 32 with full support of various processor interfaces
including the Pentium™ and PowerPC™. The flow-through burst archi-
tecture provides cost-effective 2-1-1-1 performance for processors up to
50 MHz.
The IDT71V433 SRAM contains write, data-input, address and
control registers. There are no registers in the data output path (flow-
through architecture). Internal logic allows the SRAM to generate a
self-timed write based upon a decision which can be left until the
extreme end of the write cycle.
The burst mode feature offers the highest level of performance to
the system designer, as the IDT71V433 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from
the array after a clock-to-data access time delay from the rising clock
edge of the same cycle. If burst mode operation is selected (ADV=LOW),
the subsequent three cycles of output data will be available to the
user on the next three rising clock edges. The order of these three
addresses will be defined by the internal burst counter and the LBO
input pin.
The IDT71V433 SRAM utilizes IDT's high-performance 3.3V
CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Pin Description
A0–A14
CE
CS0, CS1
OE
GW
BWE
BW1–BW4
CLK
ADV
Address Inputs
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock Input
Burst Address Advance
ADSC
ADSP
Address Status (Cache Controller)
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O0–I/O31
Data Input/Output
VDD, VDDQ
Co re and I/O Power Supply (3.3V)
VSS, VSSQ
Array Ground, I/O Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Power
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
3729 tbl 01
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
1
©2000 Integrated Device Technology, Inc.
AUGUST 2001
DSC-3729/04