IDT71V3548S Datasheet, PDF (1/26 Pages) Integrated Device Technology – 256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs

256K x 18
3.3V Synchronous ZBT SRAM
3.3V I/O, Burst Counter
Pipelined Outputs
IDT71V3548S
IDT71V3548SA
Features
x _{256K x 18 memory configurations}
x _{Supports high performance system speed - 133 MHz}
(4.2 ns Clock-to-Data Access)
x _ZBTTM _{Feature - No dead cycles between write and read}
cycles
x _{Internally synchronized output buffer enable eliminates the}
need to control OE
x _{Single R/W (READ/WRITE) control pin}
x _{Positive clock-edge triggered address, data, and control}
signal registers for fully pipelined applications
x _{4-word burst capability (interleaved or linear)}
x _{Individual byte write (BW1 - BW4) control (May tie active)}
x _{Three chip enables for simple depth expansion}
x _{3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)}
x _{Optional Boundary Scan JTAG Interface (IEEE 1149.1}
compliant)
x _{Packaged in a JEDEC standard 100-pin plastic thin quad}
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT^TM, or
Zero Bus Turnaround.
Pin Description Summary
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3548 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3548
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
The IDT71V3548 has an on-chip burst counter. In the burst
mode, the IDT71V3548 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. The LBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V3548 SRAMs utilize IDT's latest high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm 100- pin
plastic thin quad flatpack (TQFP) as well as a 119 ball grid array (BGA)
and 165 fine pitch ball grid array (fBGA).
A0-A17
CE1, CE2, CE2
OE
R/W
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Input
Synchronous
Input
Synchronous
Input
Asynchronous
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
ADV/LD
LBO
Clock
Advance burst addre ss / Load new address
Linear / Interleaved Burst Order
Input
N/A
Input
Synchronous
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
TRST
Test Data Output
JTAG Reset (Optional)
Output
Input
Synchronous
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O0-I/O15, I/OP1-I/OP2
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
Static
VSS
Ground
©2002 Integrated Device Technology, Inc.
Supply
1
Static
5296 tbl 01
MAY 2002
DSC-5296/03