IDT71V321S Datasheet, PDF (1/14 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT

HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
IDT71V321S/L
IDT71V421S/L
.eatures
x _{High-speed access}
– Commercial: 25/35/55ns (max.)
– Industrial: 25ns (max.)
x _{Low-power operation}
– IDT71V321/IDT71V421S
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71V321/V421L
— Active: 325mW (typ.)
— Standby: 1mW (typ.)
x _{Two INT flags for port-to-port communications}
x _{MASTER IDT71V321 easily expands data bus width to 16-}
or-more-bits using SLAVE IDT71V421
x _{On-chip port arbitration logic (IDT71V321 only)}
x _{BUSY output flag on IDT71V321; BUSY input on IDT71V421}
x _{Fully asynchronous operation from either port}
x _{Battery backup operation—2V data retention (L only)}
x _{TTL-compatible, single 3.3V power supply}
x _{Available in 52-pin PLCC, 64-pin TQFP and STQFP}
packages
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
.unctional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL^(1,2)
A10L
A0L
I/O
Control
I/O
Control
Address
Decoder
11
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
11
CER
OER
R/WR
I/O0R-I/O7R
BUSYR^(1,2)
A10R
A0R
INTL⁽²⁾
NOTES:
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.
2. BUSY and INT are totem-pole outputs.
1
©2001 Integrated Device Technology, Inc.
INTR⁽²⁾
3026 drw 01
AUGUST 2001
DSC-3026/8