IDT71V256SA Datasheet, PDF (1/6 Pages) Integrated Device Technology – LOW POWER 3.3V CMOS FAST SRAM 256K (32K x 8-BIT)

Integrated Device Technology, Inc.
LOW POWER
3.3V CMOS FAST SRAM
256K (32K x 8-BIT)
IDT71V256SA
FEATURES
• Ideal for high-performance processor secondary cache
• Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
• Fast access times:
— Commercial: 10/12/15/20ns
— Industrial: 15ns
• Low standby current (maximum):
— 2mA full standby
• Small packages for space-efficient layouts:
— 28-pin 300 mil SOJ
— 28-pin 300 mil plastic DIP (Commercial only)
— 28-pin TSOP Type I
• Produced with advanced high-performance CMOS
technology
• Inputs and outputs are LVTTL-compatible
• Single 3.3V(±0.3V) power supply
DESCRIPTION
The IDT71V256SA is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology.
The IDT71V256SA has outstanding low power character-
istics while at the same time maintaining very high perfor-
mance. Address access times of as fast as10 ns are ideal for
3.3V secondary cache in 3.3V desktop designs.
When power management logic puts the IDT71V256SA in
standby mode, its very low power characteristics contribute to
extended battery life. By taking CS HIGH, the SRAM will
automatically go to a low power standby mode and will remain
in standby as long as CS remains HIGH. Furthermore, under
full standby mode (CS at CMOS level, f=0), power consump-
tion is guaranteed to always be less than 6.6mW and typically
will be much smaller.
The IDT71V256SA is packaged in 28-pin 300 mil SOJ, 28-
pin 300 mil plastic DIP, and 28-pin 300 mil TSOP Type I
packaging.
FUNCTIONAL BLOCK DIAGRAM
A0
ADDRESS
DECODER
A14
I/O0
INPUT
DATA
CIRCUIT
I/O7
CS
OE
CONTROL
WE
CIRCUIT
262,144 BIT
MEMORY ARRAY
I/O CONTROL
VCC
GND
3101 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997 Integrated Device Technology, Inc.
MAY 1997
DSC-3101/04
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