IDT71V2546S_11 Datasheet, PDF (1/21 Pages) Integrated Device Technology – 3.3V Synchronous ZBT SRAM

128K x 36
3.3V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71V2546S/XS
Features
◆ _{128K x 36 memory configurations}
◆ _{Supports high performance system speed - 150 MHz}
(3.8 ns Clock-to-Data Access)
◆ _ZBTTM _{Feature - No dead cycles between write and read}
cycles
◆ _{Internally synchronized output buffer enable eliminates the}
need to control OE
◆ _{Single R/W (READ/WRITE) control pin}
◆ _{Positive clock-edge triggered address, data, and control}
signal registers for fully pipelined applications
◆ _{4-word burst capability (interleaved or linear)}
◆ _{Individual byte write (BW1 - BW4) control (May tie active)}
◆ _{Three chip enables for simple depth expansion}
◆ _{3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)}
◆ _{Packaged in a JEDEC standard 100-pin plastic thin quad}
flatpack (TQFP) and 119 ball grid array (BGA)
Description
The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
Thus, they have been given the name ZBT^TM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546 contains data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2546 to be
suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2546 has an on-chip burst counter. In the burst mode, the
IDT71V2546 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. The LBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546 SRAM utilize IDT's latest high-performance CMOS
process and is packaged in a JEDEC standard 14mm x 20mm 100-pin
thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).
Pin Description Summary
A0-A16
CE1, CE2, CE2
OE
R/W
CEN
BW1, BW2, BW3, BW4
CLK
ADV/LD
LBO
ZZ
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
VSS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
Static
Static
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©2011 Integrated Device Technology, Inc.
APRIL 2011
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