IDT71V124SA_14 Datasheet, PDF (1/8 Pages) Integrated Device Technology – 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power and Ground Pinout

3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
IDT71V124SA
Features
◆ _{128K x 8 advanced high-speed CMOS static RAM}
◆ _{JEDEC revolutionary pinout (center power/GND) for}
reduced noise
◆ _{Equal access and cycle times}
– Commercial: 10/12/15ns
– Industrial: 12/15ns
◆ _{One Chip Select plus one Output Enable pin}
◆ _{Inputs and outputs are LVTTL-compatible}
◆ _{Single 3.3V supply}
◆ _{Low power consumption via chip deselect}
◆ _{Available in a 32-pin 300- and 400-mil Plastic SOJ, and}
32-pin Type II TSOP packages.
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs. The JEDEC center power/GND pinout reduces noise
generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns available. All bidirectional
inputs and outputs of the IDT71V124 are LVTTL-compatible and operation
is from a single 3.3V supply. Fully static asynchronous circuitry is used;
no clocks or refreshes are required for operation.
Functional Block Diagram
A0
•
•
•
ADDRESS
•
•
•
DECODER
A16
1,048,576-BIT
MEMORY ARRAY
I/O0 - I/O7
8
8
WE
OE
CONTROL
CS
LOGIC
I/O CONTROL
8
.
3873 drw 01
1
© 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2013
DSC-3873/11