IDT71V016SA_13 Datasheet, PDF (1/9 Pages) Integrated Device Technology – 3.3V CMOS Static RAM

3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71V016SA
Features
◆ _{64K x 16 advanced high-speed CMOS Static RAM}
◆ _{Equal access and cycle times}
— Commercial: 10/12/15/20ns
— Industrial: 10/12/15/20ns
◆ _{One Chip Select plus one Output Enable pin}
◆ _{Bidirectional data inputs and outputs directly}
LVTTL-compatible
◆ _{Low power consumption via chip deselect}
◆ _{Upper and Lower Byte Enable Pins}
◆ _{Single 3.3V power supply}
◆ _{Available in 44-pin Plastic SOJ, 44-pin TSOP, and}
48-Ball Plastic FBGA packages
Functional Block Diagram
Output
OE
Enable
Buffer
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using high-perfomance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71V016 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V016 are LVTTL compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ,
a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
A0 – A15
Address
Buffers
Chip
CS
Enable
Buffer
Write
WE
Enable
Buffer
Row / Column
Decoders
64K x 16
Memory
Array
8
Sense
16
Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
I/O15
8
I/O8
I/O7
8
I/O0
BHE
BLE
Byte
Enable
Buffers
1
© 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
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AUGUST 2013
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