IDT71V016 Datasheet, PDF (1/9 Pages) Integrated Device Technology – 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)

3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71V016
Features
Description
◆ _{64K x 16 advanced high-speed CMOS Static RAM}
The IDT71V016 is a 1,048,576-bit high-speed Static RAM
◆ _{Commercial (0° to +70°C) and Industrial (–40°C to +85°C) organized as 64K x 16. It is fabricated using IDT’s high-perfomance,}
◆ _{Equal access and cycle times}
high-reliability CMOS technology. This state-of-the-art technology,
— Commercial and Industrial: 15/20ns
combined with innovative circuit design techniques, provides a
◆ _{One Chip Select plus one Output Enable pin}
cost-effective solution for high-speed memory needs.
◆ _{Bidirectional data inputs and outputs directly}
The IDT71V016 has an output enable pin which operates as fast
LVTTL-compatible
as 7ns, with address access times as fast as 12ns. All bidirectional
◆ _{Low power consumption via chip deselect}
◆ _{Upper and Lower Byte Enable Pins}
◆ _{Single 3.3V (±0.3V) power supply}
◆ _{Available in 44-pin Plastic SOJ and 44-pin TSOP}
E _package.
N ^C _{Functional Block Diagram}
I _{N A Output}
T ^{E OE}
Enable
S _{S Buffer}
inputs and outputs of the IDT71V016 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous circuitry
is used, requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin
Plastic SOJ and 44-pin TSOP Type II.
AR ^{SC 016 IGN} _A0-A15
Address
Buffers
P _{LE 71VDES Chip}
O CS
Enable
R _Buffer
BS _{RDE NEW Write}
WE
Enable
O OFOR ^Buffer
Row / Column
Decoders
64K x 16
Memory
Array
8
Sense
16
Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
I/O15
8
I/O8
I/O7
8
I/O0
BHE
Byte
Enable
Buffers
BLE
©2000 Integrated Device Technology, Inc.
3211 drw 01
AUGUST 2000
1
DSC-3211/08