IDT71T75602_12 Datasheet, PDF (1/23 Pages) Integrated Device Technology – Synchronous ZBT SRAMs

512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71T75602
IDT71T75802
Features
• 512K x 36, 1M x 18 memory configurations
• Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
• ZBT^TM Feature - No dead cycles between write and read
cycles
• Internally synchronized output buffer enable eliminates the
need to control OE
• Single R/W (READ/WRITE) control pin
• Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
• 4-word burst capability (interleaved or linear)
• Individual byte write (BW1 - BW4) control (May tie active)
• Three chip enables for simple depth expansion
• 2.5V power supply (±5%)
• 2.5V I/O Supply (VDDQ)
• Power down controlled by ZZ input
• Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
• Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Description
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs. They are designed to eliminate dead
bus cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT^TM, or Zero
Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71T75602/802 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable CEN pin allows operation of the IDT71T75602/802
to be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
Pin Description Summary
A0-A19
Address Inputs
CE1, CE2, CE2
Chip Enables
OE
Output Enable
R/W
Read/Write Signal
CEN
Clock Enable
BW1, BW2, BW3, BW4
Individual Byte Write Selects
CLK
Clock
ADV/LD
Advance burst address / Load new address
LBO
Linear / Interleaved Burst Order
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock
TDO
Test Data Input
TRST
JTAG Reset (Optional)
ZZ
Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS
Ground
1
©2012 Integrated Device Technology, Inc.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Synchronous
Static
Static
5313 tbl 01
APRIL 2012
DSC-5313/10