IDT71P79204 Datasheet, PDF (1/23 Pages) Integrated Device Technology – 18Mb Pipelined DDR™II SIO SRAM Burst of 2

18Mb Pipelined
DDR™II SIO SRAM
Burst of 2
IDT71P79204
IDT71P79104
IDT71P79804
IDT71P79604
Features
◆ 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
◆ Separate, Independent Read and Write Data Ports
- Supports concurrent transactions
◆ Dual Echo Clock Output
◆ 2-Word Burst on all SRAM accesses
◆ Multiplexed Address Bus
- One Read or one Write request per clock cycle
◆ DDR (Double Data Rate) Data Bus
- Two word burst data per clock
◆ Depth expansion through Control Logic
◆ HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V
to 1.9V.
◆ Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70 ohms
◆ 1.8V Core Voltage (VDD)
◆ 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package
◆ JTAG Interface
Description
The IDT DDRII^TM Burst of two SIO SRAMs are high-speed syn-
chronous memories with independent, double-data-rate (DDR), read
and write data ports with two data items passed with each read or write.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the DDRII SIO are unidirectional and can be optimized
for signal integrity at very high bus speeds. Memory bandwidth is higher
than DDR SRAM with bi-directional data buses as separate read and
write ports eliminate bus turn around cycle. Separate read and write
ports also enable easy depth expansion. Each port can be selected
independantly with a R/W input shared among all SRAMs and provide
a new LD load control signal for each bank. The DDRII SIO has scal-
able output impedance on its data output bus and echo clocks, allowing
the user to tune the bus for low noise and high performance.
The DDRII SIO has a single SDR address bus with multiplexed
read and write addresses. The read/write and load control inputs are
received on the first half of the clock cycle. The byte and nibble write
signals are received on both halves of the clock cycle simultaneously
with the data they are controlling on the data input bus.
The DDRII SIO has echo clocks, which provide the user with a
clock that is precisely timed to the data output, and tuned with matching
impedance and signal quality. The user can use the echo clock for
downstream clocking of the data. Echo clocks eliminate the need for the
user to produce alternate clocks with precise timing, positioning, and
signal qualities to guarantee data capture. Since the echo clocks are
Functional Block Diagram
(Note1)
D
DATA
REG
DATA
REG
(Note1)
SA ^(Note2)
ADD
REG
(Note2)
LD
R/W
BWx
(Note3)
CTRL
LOGIC
WRITE DRIVER
18M
MEMORY
ARRAY
(Note4)
(Note4)
(Note1) _Q
K
CLK
CQ
K
GEN
CQ
C
SELECT OUTPUT CONTROL
C
Notes:
6432 drw 16
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
NOVEMBER 2005
1
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.DSC-6432/01