IDT71P74204 Datasheet, PDF (1/22 Pages) Integrated Device Technology – 18Mb Pipelined QDR II SRAM Burst of 4

Advance
18Mb Pipelined
QDR™II SRAM
Burst of 4
Information
IDT71P74204
IDT71P74104
IDT71P74804
Features
Description
IDT71P74604
x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
The IDT QDRII^TM Burst of four SRAMs are high-speed synchronous
x Separate, Independent Read and Write Data Ports
memories with independent, double-data-rate (DDR), read and write
- Supports concurrent transactions
data ports. This scheme allows simultaneous read and write access for
x Dual Echo Clock Output
the maximum device throughput, with four data items passed with each
x 4-Word Burst on all SRAM accesses
read or write. Four data word transfers occur per clock cycle, providing
x Multiplexed Address Bus One Read or One Write request quad-data-rate (QDR) performance. Comparing this with standard SRAM
per clock cycle
common I/O (CIO), single data rate (SDR) devices, a four to one in-
x DDR (Double Data Rate) Data Bus
crease in data access is achieved at equivalent clock speeds. Consider-
- Four word burst data per two clock cycles on
ing that QDRII allows clock speeds in excess of standard SRAM de-
each port
vices, the throughput can be increased well beyond four to one in most
- Four word transfers per clock cycle
applications.
x Depth expansion through Control Logic
Using independent ports for read and write data access, simplifies
x HSTL (1.5V) inputs that can be scaled to receive signals system design by eliminating the need for bi-directional buses. All buses
from 1.4V to 1.9V.
associated with the QDRII are unidirectional and can be optimized for
x Scalable output drivers
signal integrity at very high bus speeds. The QDRII has scalable output
- Can drive HSTL, 1.8V TTL or any voltage level impedance on its data output bus and echo clocks, allowing the user to
from 1.4V to 1.9V.
tune the bus for low noise and high performance.
- Output Impedance adjustable from 35 ohms to 70
The QDRII has a single SDR address bus with read addresses and
ohms
write addresses multiplexed. The read and write addresses interleave
x 1.8V Core Voltage (VDD)
with each occurring a maximum of every other cycle. In the event that no
x 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package
operation takes place on a cycle, the subsequest cycle may begin with
x JTAG Interface
either a read or write. During write operations, the writing of individual
bytes may be blocked through the use of byte or nibble write control
signals.
The QDRII has echo clocks, which provide the user with a clock
Functional Block Diagram
D
(Note1)
DATA
REG
(Note2)
SA
ADD ^(Note2)
REG
R
CTRL
W
(Note3)
LOGIC
BWx
WRITE DRIVER
18M
MEMORY
ARRAY
(Note1)
Q
K
CLK
CQ
K
GEN
CQ
C
SELECT OUTPUT CONTROL
C
6111 drw16
Notes
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x8 and x9, 18 address signal lines for x18, and 17 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write”
and there are 2 signal lines.
MARCH
2004
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ DSC-6111/00