IDT7133SA Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS

HIGH SPEED
2K X 16 DUAL-PORT
SRAM
IDT7133SA/LA
IDT7143SA/LA
Features
x _{High-speed access}
– Military: 25/35/45/55/70/90ns (max.)
– Industrial: 25/35/55ns (max.)
– Commercial: 20/25/35/45/55/70/90ns (max.)
x _{Low-power operation}
– IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
– IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
x _{Versatile control for write: separate write control for lower}
and upper byte of each port
x _{MASTER IDT7133 easily expands data bus width to 32 bits}
or more using SLAVE IDT7143
x _{On-chip port arbitration logic (IDT7133 only)}
x _{BUSY output flag on IDT7133; BUSY input on IDT7143}
x _{Fully asynchronous operation from either port}
x _{Battery backup operation–2V data retention}
x _{TTL-compatible; single 5V (±10%) power supply}
x _{Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-}
pin TQFP
x _{Military product compliant to MIL-PRF-38535 QML}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
Description
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port
RAM or as a “MASTER” Dual-Port RAM together with the IDT7143
“SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider
Functional Block Diagram
R/WLUB
CEL
R/WRUB
CER
R/WLLB
OEL
R/WRLB
OER
I/O8L - I/O15L
I/O0L - I/O7L
BUSYL⁽¹⁾
A10L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
11
CEL
MEMORY
ARRAY
ARBITRATION
LOGIC
(IDT7133 ONLY)
ADDRESS
DECODER
11
CER
I/O8R - I/O15R
I/O0R - I/O7R
BUSYR⁽¹⁾
A10R
A0R
NOTE:
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
1
©2000 Integrated Device Technology, Inc.
2746 drw 01
JUNE 2000
DSC 2746/11