IDT71321SA_08 Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM

HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
IDT71321SA/LA
IDT71421SA/LA
Features
◆ _{High-speed access}
– Commercial: 20/25/35/55ns (max.)
– Industrial: 25/55ns (max.)
◆ _{Low-power operation}
– IDT71321/IDT71421SA
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71321/421LA
— Active: 325mW (typ.)
— Standby: 1mW (typ.)
◆ _{Two INT flags for port-to-port communications}
◆ _{MASTER IDT71321 easily expands data bus width to 16-or-}
more-bits using SLAVE IDT71421
◆ _{On-chip port arbitration logic (IDT71321 only)}
◆ _{BUSY output flag on IDT71321; BUSY input on IDT71421}
◆ _{Fully asynchronous operation from either port}
◆ _{Battery backup operation – 2V data retention (LA only)}
◆ _{TTL-compatible, single 5V ±10% power supply}
◆ _{Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP}
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL^(1,2)
A10L
A0L
I/O
Control
I/O
Control
Address
Decoder
11
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
11
CER
OER
R/WR
I/O0R-I/O7R
BUSYR^(1,2)
A10R
A0R
INTL⁽²⁾
NOTES:
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
1
©2008 Integrated Device Technology, Inc.
INTR⁽²⁾
2691 drw 01
OCTOBER 2008
DSC-2691/13