IDT7130SA55JI Datasheet, PDF (1/21 Pages) Integrated Device Technology – HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
IDT7130SA/LA
IDT7140SA/LA
Features
◆ _{High-speed access}
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
◆ _{Low-power operation}
– IDT7130/IDT7140SA
— Active: 550mW (typ.)
— Standby: 5mW (typ.)
– IDT7130/IDT7140LA
— Active: 550mW (typ.)
— Standby: 1mW (typ.)
◆ _{MASTER IDT7130 easily expands data bus width to 16-or-}
more-bits using SLAVE IDT7140
◆ _{On-chip port arbitration logic (IDT7130 Only)}
◆ _{BUSY output flag on IDT7130; BUSY input on IDT7140}
◆ _{INT flag for port-to-port communication}
◆ _{Fully asynchronous operation from either port}
◆ _{Battery backup operation–2V data retention (LA only)}
◆ _{TTL-compatible, single 5V ±10% power supply}
◆ _{Military product compliant to MIL-PRF-38535 QML}
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin}
PLCC, and 64-pin STQFP and TQFP
◆ _{Green parts available, see ordering information}
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL^(1,2)
A9L
A0L
I/O
Control
I/O
Control
Address
Decoder
10
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
10
CER
OER
R/WR
,
I/O0R-I/O7R
BUSYR(1,2)
A9R
A0R
INTL(2)
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
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©2013 Integrated Device Technology, Inc.
INTR(2)
2689 drw 01
JANUARY 2013
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