IDT70V9389L_14 Datasheet, PDF (1/19 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
64K x18/x16
SYNCHRONOUS PIPELINED ^{IDT70V9389/289L}
Š ^{DUAL-PORT STATIC RAM}
Features:
◆ _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed clock to data access}
– Commercial: 7.5/9/12ns (max.)
– Industrial: 9ns (max.)
◆ _{Low-power operation}
– IDT70V9389/289L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
◆ _{Flow-Through or Pipelined output mode on either port via}
the FT/PIPE pins
◆ _{Counter enable and reset features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{LVTTL- compatible, single 3.3V (±0.3V) power supply}
Functional Block Diagram
◆ _{Full synchronous operation on both ports}
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output
mode
◆ _{Separate upper-byte and lower-byte controls for}
multiplexed bus and bus matching compatibility
◆ _{Industrial temperature range (–40°C to +85°C) is}
available for selected speeds
◆ _{Available in a 128-pin Thin Quad Flatpack (TQFP) and}
100-pin Thin Quad Flatpack (TQFP)
◆ _{Green parts available, see ordering information}
R/WL
UBL
CE0L
CE1L
1
0
0/1
LBL
OEL
R/WR
UBR
CE0R
1
0
CE1R
0/1
LBR
OER
FT/PIPEL
I/O9L-I/O17L⁽²⁾
I/O0L-I/O8L⁽¹⁾
A15L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 ^{1b 0b} b a ^{1a 0a}
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
0a 1a
a
b0b ^1b
0/1
Counter/
Address
Reg.
FT/PIPER
I/O9R-I/O17R⁽¹⁾
I/O0R-I/O8R⁽¹⁾
A15R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4856 drw 01
NOTES:
1. I/O0X - I/O7X for IDT70V9289.
2. I/O8X - I/O15X for IDT70V9289.
1
©2014 Integrated Device Technology, Inc.
MARCH 2014
DSC-4856/8